Synclock – E Driver

Synclock-E is a highly integrated timing card FPGA core for systems with SONET/SDH or Synchronous Ethernet ports. The Synclock-E SW driver will serve the Synclock-E FPGA core, developed in the Client premises with the main purpose to replace the current third party device DS3102.

Client Profile
An industry Leader in access solutions for data telecommunications applications.

Salient Product Features
The Synclock-E has eight input clocks pins (IC1 to IC8). The device can output different clock frequencies on 2 output clock pins OCI and OC2. There are two separate DPLLs in the device: the high performance T0 DPLL and the simpler the T4 DPLL.

    Some of the major features supported by the project implementation are listed below.

  1. The driver works with PSOS and VxWorks RTOS.
  2. The driver provides the same external APIs with the same prototypes as the current DS3102 driver.
  3. The driver covers full functionality provided by Synclock-E core.
  4. Hardware adaptation layer is modified for Synclock-E and this layer act as the interface between the driver instance and the system interface layer.
  5. Three types of configurations are supported:
    • Fixed
    • Project dependent
    • Run-time.
      For the fixed configuration parameters specified by the client the driver should once initialize them. For project dependent configuration the driver should provide compilation time configuration (macro definitions) and for run time configuration parameters the driver should provide appropriate APIs.
  6. The driver handles the interrupts generated by the FPGA core. Interrupt Service Routine is responsible for processing hardware interrupt
    from the device. ISR is implemented as aISR-task combination in which the bottom half of the ISR will be implemented as a task. The
    interrupt cause and data will be informed to the interested task using a message queue.
  7. Memory Access -The Synclock-E is connected to the CPU over its parallel bus.The driver provides required protection for multi register
    field operations to ensure that the bytes of the field remain consistent.
  8. Input Clock – The eight input clocks accepts any multiple of 2 kHz from 8 kHz to 125 MHz.
  9. Output Clock – The output frequencies supported by OC1 and OC2 are
         OC1 – 8 kHz, 1.544 MHz, 2.048 MHz, 10 MHz, 19.44 MHz and 25 MHz
         OC2 – 8 kHz, 1.544 MHz and 2.048 MHz.

  10. Frequency Monitoring – Except Soft Frequency Monitoring all other frequency monitoring is supported by driver. Configurable threshold is
    supported for Hard Frequency Monitoring.
  11. Revertive mode – Both T0 DPLL and T4 DPLL operates in revertive mode.
  12. An additional API for resetting the Synclock-E is provided..
  13. Debug menus are used for testing purpose.

    Key Customer Value

  1. Synclock implementation helped the client to achieve a synchronized physical Ethernet layer thereby reducing the packet loss and packet delay when the customer’s device is used in the network.